A New Approach to Design TPG for Low Power Testing Applications

VLSI circuit’s encounters are rapidly many challenging tasks of semiconductor manufacturing along operating with gigahertz range of frequencies. These challenges are include keeping peak power dissipation and the application time within limits. In this Paper we are proposes a new approach of low power Test Pattern Generator (TPG) designed by modifying parallel Linear Feedback Shift Register (Parallel-LFSR) deployed on Circuit under Test (CUT) to slenderize the dynamic power consumption by CUT. To propose a new output sequence of parallel-LFSR to design a low-power test pattern generator for Built In Self Test (BIST) achieve reduce the overall switching activity in CUT. New architecture for LFSR with parallel mechanism reduces the power significantly at scans. The experimental result shows a best power reduction by low power TPG than compared to LFSR. The proposed work is design and implemented using Verilog HDL and Xilinx ISE.